Job Responsibilities:

• Development of low power design techniques for CMOS standard cell based devices targeting process nodes of 130nm and below.
• Evaluation of externally developed IP such as standard cell libraries and memories.
• Physical design from netlist to GDS2 including full-chip power analysis, power-grid design, clock-tree design, parasitic extraction and timing closure, noise analysis and signal-integrity.

Skills and Experience:

• Minimum 2 years related experience, either in industry or academia.
• Strong understanding of transistor-level, gate-level and interconnect-level CMOS circuit design and process technology.
• Strong understanding of circuit design techniques related to standard-cells and memories, and reducing both leakage and dynamic power.
• Experience with 90nm and 65nm technologies highly desirable.
• Familiarity with all aspects of IC design including floor planning, power planning, clock tree insertion, place and route, parasitic extraction, noise and signal integrity analysis and repair, ECO, LVS and DRC.
• Proficient in script writing: Perl, tcl, make, Linux/Unix shell script.
• Strong written and oral communication skills.
• MSEE, PhD preferred.